The present invention relates to a multi-processor and method for controlling an access to a translation look-aside buffer (TLB), and more particularly to a multi-processor system and method for controlling an access to a translation look-aside buffer which has been invalidated (e.g., updated).
As is well-known, virtual memory provides a virtual (logical) address space using an auxiliary storage to save a sufficiently wide address space beyond the physical capacity limit of a main memory. The virtual address space is assigned to the real (physical) address of the main memory. Generally, the virtual memory concept makes the normal-sized main memory appear to the user as large as the virtual-address space (e.g., represented by a register or the like holding the virtual address), while still appearing to run at essentially the speed of the actual memory.
In a virtual memory system with paged segmentation, virtual memory areas are divided into variable-size blocks called "segments", and each segment is divided into fixed-size blocks called "pages". Active blocks are placed on (e.g., dynamically paged into) the main memory, while the remaining blocks are placed on the auxiliary storage.
Referring to FIG. 1, each logical address comprises three parts: a segment address, a page address, and a displacement. The segment address is a relative address in a segment table. The page address is a relative address in a page table. The displacement is a relative address in a page. The segment table stores segment descriptors specifying page tables. The page table stores page descriptors specifying pages.
A translation look-aside buffer (TLB) of a processor is a special type of cache for storing (e.g., registering) pairs of logical addresses and physical addresses. Thus, a logical address will be stored with a corresponding physical address as a pair. The TLB of the processor is referenced each time the main memory is accessed, thereby to perform the translation from a logical address to a physical address. When an entry in the TLB must be deallocated (e.g., at the end of a process), the entry is invalidated (e.g., deleted or updated).
In a conventional multi-processor system with virtual memory, when a processor issues a message to invalidate an entry in its TLB, the message is sent to all of the TLBs of the processors in the multi-processor system. During the invalidating process, prior to performing other processes, other processors must wait for completion of the TLB entry invalidating process.
Thus, normal operations cannot be performed until the TLB entry invalidating operation is completed, since other processors are in "waiting" (pause) states. This waiting by the other processors lowers the system performance.